Device for controlling display output by micro-program

ABSTRACT

A display device is incorporated in a desk top calculator or the like to visually display the numeric information output stored in an indicating register. Such displaying of the numeric information output is performed under the control of the microcontrol commands and micro-digit information which both read out of the read-only memory.

United States Patent [191 Shimizu et al.

[451 Dec. 31, 1974 1 DEVICE FOR CONTROLLING DISPLAY OUTPUT BY MICRO-PROGRAM [75] Inventors: Mitsuo Shimizu, Yokohama; lchiro Sado, Tokyo, both of Japan [73] Assignee: Canon Kabushiki Kaisha, Tokyo,

Japan [22] Filed: Nov. 2, 1972 [21] Appl. No.: 303,013

[30] Foreign Application Priority Data [58] Field of Search 340/324 R, 324 AD, 168 S Primary Examiner.lohn W. Caldwell Assistant Examiner-Marshall M. Curtis Attorney, Agent, or Firm-Fitzpatrick, Cella, Harper & Scinto [57] ABSTRACT A display device is incorporated in a desk top calculator or the like to visually display the numeric information output stored in an indicating register. Such displaying of the numeric information output is performed under the control of the micro-control commands and micro-digit information which both read out of the read-only memory.

[561 References and 4 Claims, 5 Drawing Figures UNITED STATES PATENTS 3,396,377 8/1968 Strout 340/324 AD n READ ONLY MEMORY l DIGIT 2 INFORMATION BUFFER DISPLAY UNIT 'i NUMERICY INFORMATION BUFFER I? COINCIDENCE ClRCUlT T I? y' 18 DECIMAL INDICATING ARITHMETIC 802%; REGISTER UNIT 2 CONTROL SIGNAL iNFORMATlON SIGNAL PATENTEDBEBB I I914 |NFORMATION SIGNAL SHEET 10F 4 FIG. I -II READ ONLY MEMORY OIOIT 2 INFORMATION BUFFER DISPLAY UNIT NuMERIc' 1 INFORMATION BUFFER I I? COINCIDENCE CIRCUIT I? I8 DECIMAL INDICATING ARITHMETIC 'BQ'Q' REGISTER UNIT CONTROL SIGNAL PIIIEIITFITITR I I914 33558.19?

sum 3 BF 4 DERIVE DECIMAL POINT 3 INFORMATION FROM I INDICATING REGISTER OERIvE n NUMERlC INFORMATION FROM INDICATING REGISTER I DIGIT NUMERIC INFORMATION O FFI2OI NO SET 1 I REAO OUT nIh DIGIT INFORMATION FROM ROM COINC I DENCE DER|VE(rI--II NUMERIC INFORMATION FROM INDICATING REGISTER I EXECUTION OF THE sAME OPERATION As IN MARK DERIVE LSD NUMERIC INFORMATION FROM INDICATING REGISTER FFIZOI RESET DEVICE FOR CONTROLLING DISPLAY OUTPUT BY MICRO-PROGRAM BACKGROUND OF THE INVENTION The present invention relates to a device for controlling, by the micro-program stored in a read-only memory, the display outputs, which are stored in a register, to be displayed by a display unit of a desk top calculator, or the like.

The recent large scale integrated circuits make it possible to design desk top calculators very compact in size and light in weight. The large scale integrated circuits consisting of, for example, MOS transistors are used in the memory, arithmetic unit, arithmetic operation convtrol unit, output control unit and the like in such desk top calculators. The control unit generally occupies the largest space, whereas the memory occupies the smallest space, because the former generally comprises a plurality of gates and a'plurality of flip-flops, whereas the latter comprises only a shift register or matrix, which is best adapted to be manufactured as a large scale integrated circuit.

SUMMARY OF THE INVENTION The present invention is directed to incorporating a display output control unit for deriving the numeric information stored in an indicating register and a digit information signal generating unit in a control unit, thereby making full use of the advantages of the large scale integrated circuits.

In order to provide a high-class desk top calculator capable of accomplishing various functions by the recently developed micro-program, the present invention further intends to provide a device for controlling the numeric information output stored in an indicating register by the micro-program stored in a read-only memory. In desk top calculators, there has generally been used a display unit of the type comprising a plurality of gaseous-discharge lamps, or the like, which are arrayed and turned on to dynamically display the numeric information. In this case the digit pulses, having a predetermined pulse width, must be applied to the display unit so that there must be provided a first counter for counting the clock pulses generated by a clock pulse generator, a second counter for counting one for every four output signals from the first counter and a digitpulse generator. As a result the number of component parts is considerably increased, and the period of the digit pulse is limited to that of the clock pulse, because the digit pulse generator is generally actuated in response to the clock pulses. The clock pulses also determine the speed of the arithmetic operations so that the period of the clock pulses must be shortened in order to increase the speed of operation. However, when the period of the clock pulses is shortened, the period of the digit pulses is also shortened so that digit pulses, having a sufficient pulse width to dynamically turn on the indicating lamps or the like, cannot be obtained. That is, when the operation speed is increased. the ON time of the indicating lamp becomes shorter so that a display, with a desired brightness, cannot be attained because of the delay in discharge, or the like. Therefore, unless a specially designed digit pulse generator and an indicating lamp driving circuit for turning on the indicating lamp with a desired brightness are provided,

the display of the numeric information becomes impossible.

According to the present invention., the above and other defects and problems encountered in the prior art display units incorporated in a desk top calculator or the like, may be overcome by controlling the numeric information output from an indicating register, by the micro-control commands and by the micro-digit information, which both read out of the read-only memory. According to the present invention, a circuit for supressing the insignificant zeros or digits, as well as a circuit for displaying a decimal point, may be designed, compact in size and simple in construction.

The above and other objects, features and advantages of the present invention will become more apparent from the following description of one preferred embodiment thereof taken in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a fundamental block diagram of one preferred embodiment of the present invention;

FIG. 2 is a detailed circuit diagram of the device shown in FIG. 1;

FIG. 3 is a flow chart of the commands stored in a read-only memory;

FIG. 4 is a circuit diagram of one example of a readonly memory; and 7 FIG. 5 shows the waveforms of the command signals derived from the read-only memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 there is illustrated in block diagram from a preferred embodiment of the present invention, that includes a read-only memory 11 in wlii cliis stored output control commands and digit information in the form of micro-commands. In this specification the term micro-commands" is used to refer to those simple and fundamental commands, the combinations of which constitute the micro-commands such as ADD, DIVIDE, PRINT, etc. The readonly memory 11 may comprise a diode matrix. The digit information from the read-only memory 11 is temporarily stored in a digit information buffer memory 12. A display unit 13 comprises an array of indicating .lamps in the instant embodiment, but any other suitable indicating device such as photo-diodes or liquid crystal may be used. Alternatively, a printer may be used instead of the display unit 13 when the content stored in the read-only memory 11 is appropriately changed. The numeric information to be displayed, which is stored in an indicating register 15, is temporarily stored in a numeric information, buffer memory 14 so as to be applied to cathode segments in the display unit 13. A digit having a decimal point is detected in the numeric information stored in the indicating register 15 and is temporarily stored in a decimal point buffer memory 16. The decimal point information is compared by a coindidence circuit'l7 with the digit information from the digit information buffer memory 12 so that when they coincide with each other the decimal point may be displayed by the display unit 13. The various arithmetic operations carried by an arithmetic unit 18 are controlled by the information derived from the read-only memory 11.

Next the mode of operation will be generally described.

The numeric information entered by a keyboard (not shown) of a desk top calculator, or the result of the arithmetic operations is transferred from the arithmetic unit 18 and stored in the indicating register 15, in which the numeric information is shifted to right in the ordinary manner, that is, from the most significant digit to the least significant digit. According to the present invention the numeric information in the indicating register is derived digit by digit from the most significant digit. For further information, reference is made to US. Pat. No. 3,449,726 In response to the predetermined timing signals, the numeric information in the indicating register 15 is transferred from the most significant digit into the numeric information buffer memory 14. The above method is very effective for suppressing the zero. The prior art control circuit used for this method is generally large in size and complex in construction. However, according to the present invention, the numeric information stored in the indicating register 15 is detected from the most significant digit by the read-only memory so that the circuit may be made extremely compact in size.

The numeric information in the indicating register 15 is transferred digit by digit from the most significant digit into the numeric information buffer memory l4 in response to the timing signals from the rend-only memory 11. For example, when the numeric information in the n-th digit is transferred into the numeric information buffer 14, it is decoded to energizes, selectively, predetermined numeral pattern segments out of the cathode segments in the display unit 13. Thereafter, the nth digit information is transferred into the digit information buffer 12 from the read-only memory 11 so that the anode of the n-th digit in the display unit 13 is energized. The ON time of the indicating lamp in the n-th digit may be freely adjusted depending upon the content in the read-only memory 11. For example, the ON time may be twoor three-digit time interval or oneword time interval during which the numeric informa tion in the indicating register makes one circulation.

Next, in response to the control signal from the readonly memory 11 the numeric information in the (n l th digit is transferred from the indicating register 15 into the numeric information buffer 14 so that the predetermained numeral pattern segments in the display unit 13 are energized. In this case the digit information from the read-only memory 11 is transferred into the digit information buffer memory 12 so that the anode in the (n l th digit may be energized. Thus the indicating lamp in the (n 1) th digit is turned on.

In the manner described above, the indicating lamps in all digit positions are turned on sequentially, and thereafter they are turned on again from the one in the most significant digit so that the numeric information stored in the indicating register 15 may be dynamically indicated.

The decimal point information stored in the indicating register 15 is transferred into the decimal point information buffer memory 16 in response to the control signal from the read-only memory 11, and then transferred into the coindidence circuit 17. When the decimal point information coindides with the digit information applied from the digit information buffer memory 12, the coincidence circuit 17 gives the coincidence signal to the display unit 13, thereby causing the latter to display the decimal point at the predetermined digit. From the foregoing description it is seen that according to the present invention the display output control may be effected by the circuit, which is very simple in construction.

In the detailed circuit diagram of the preferred embodiment of the present invention shown in FIG. 2, the same reference numerals are used to designate parts similar to those described with reference to FIG. 1. The digit information buffer memory 12 comprises a group of AND gates 12 and a group of flip-flops 12 The dis play unit 13 comprises an anode driver 13AD, a display unit part (1) 13A, a cathode driver 13K and a display unit part (2) 13K.

The binary coded 4-bit decimal digit information is applied to the anode driver 13A,, which, in turn, gives the output signals equal in number to the digits to be displayed by the display unit part (1) 13A. For example, when the display unit 13 has 16 digits, the anode driver 13A generates 16 output signals to be applied sequentially to the 16 anodes in the display unit part (1) 13A. The anode driver 13A,, generally comprises a decoder and an amplifier. The display unit part (1) 13A comprises a plurality of anodes equal in number to the digits to be displayed in the display unit. In response to the control signals from the read-only memory I], the anode driver l3A,,npplie1t n pulse to cnch ofthe anodes in the display unit pnrl l) IJA for in pre determined time interval. According to the present invention, a very flexible output control system may be provided because the pulse application time interval may be changed appropriately only by changing the content in the read-only memory 11. The optimum pulse application time may be selected depending upon the indicating means used in the display unit 13 such as photo-diodes or liquid crystal for example. The output control system in accordance with the present invention is advantageous because the digit information may be selectively applied for every three or four digits in order to ensure that all of the indicating lamps in the display unit 13 may be turned on. In response to the binary-coded four-bit decimal digit information, the cathode driver 13K selectively energizes the predetermined cathode segments. For example, when the cathode segments are those of a-seven-bar format or pattern, the cathode driver 13K generally comprises a binary-decimal decoder and a decimal-septimal encoder.

The decimal point information buffer memory 16 comprises a group of AND gates 16 and a group of flip-flops 16 which store the decimal point information supplied from the indicating register. The numeric information buffer memory 14 generally comprises two groups of AND gates 14 and 14 and two groups of flip-flops 14 and l4 'which store, temporarily, the numeric information from the indicating register 15. The coincidence circuit 17 generally comprises a group of AND gates 17, and NOR gates 17, which puts out a signal when, and only when, the information stored in the flip-flop group 12 in the digit information buffer memory l2 coincideswith the decimal point information stored in the flip-flop group 16 in the decimal point information buffer memory 16. The output signal is applied to the decimal point segment driver in the cathode driver IBK in the display unit 13 and to the set ter minal of a zero-suppression flip-flop 20. To the set terminal of the flipflop 20 is also applied the binarycoded four-bit decimal digit information from the flipflop group 14 in the numeric information buffer memory 14 through a numeric detection OR gate 21 and an OR gate 19.

Next, the mode of operation will be described. It is assumed that the numeric information to be displayed is stored in the indicating register 15. The numeric information, in the most significant digit, is applied to the AND gate group 14, in response to the command signal @(See FIG. 5) from the read-only memory 11 so that the AND gates are opened and the numeric information, in the most significant digit, is stored in the flipflop group 14 in the form of the binary-coded four-bit decimal digit. When the most significant digit is zero, the OR gate 21 does not put out a signal so that the flipflop 20 will not be set. The output signals of the flipflops 14 are applied to one set of input terminals of the AND gates 14;, so that when the control signal@(See FIG. 5) from the read-only memory 11 is applied to the other set of input terminals, the AND gates 14 are opened and the same numeric information is stored in the flip-flops 14,. The output signals of the flip-flops 14 are applied to the cathode driver 13K decoded and applied to the cathode group in the display unit part (2) 13K. The control signalfrom the read-only memory 11 is also applied to one set of input terminals of the AND gates 12, whereas the digit information from the read-only memory 11 is applied to the other set of terminals. As a result the AND gates 12 are opened so that the digit information is stored in the flipflops 12 The output signals of the flip-flops 12 are applied to the anode driver l3A decoded and applied to the anode group in the display unit part (2) 13A, thereby selecting and energizing the most significant digit.

However, it is preferable not to display the zero when the most significant digit is zero. For this purpose, the output signal of the flip-flop 20 is applied to one set of input terminals of the AND gates 22 whereas the output signals from the cathode driver 13K are applied to the other set of input terminals respectively so that the numeric information may be displayed only when the flip-flop 20 gives the set output signal, whereas the numeric information may not be displayed when the flipflop 20 gives the reset output signal. In the instant embodiment the most significant digit is zero so that the flip-flop 20 is not set. Thus the zero suppression may be effected.

. In a manner similar to that described above, the numeric information is detected digit by digit until the decimal digit other than zero is detected. Once the decimal digit other than zero is detected and displayed, all of the following decimal digits are displayed. Thus, the suppression of zeros can be made, only by one flip-flop.

In response to the decimal point information comman rom the read-only memory 11 (See FIG. 5) the decimal point information is transferred from the indicating register 15 through the AND gates 16, and stored in the flip-flops 16 The output signals of the flip-flops 16 are applied to one set of input terminals of the AND gates 17, in the coincidence circuit 17, and when, and only when, the output signals coincide with those applied from the digit information buffer memory 12 in response to the command signalfrom the readonly memory 11, the NOR gate 17 gives the output signal. The decimal point information may be applied to the coincidence circuit 17 from any suitable means such as a counter instead of the indicating register l5.

The output signal from the NOR gate 17 is applied to the decimal point segment selection circuit in the cathode driver 13K,, to select and energize the decimal point segment of the cathode segments in the display unit part (2) 13K. The output signal of the NOR gate 17 is also applied to the flip-flop 20, causing it to set so that the AND gates 22 are opened in order to display the decimal point even when the decimal digit in the digit in which the decimal point is displayed is zero.

FIG. 3 is a flow chart of the micro-commands stored in the read-only memory 11. It is assumed that the micro-commands derive decimal point information from indicating register" be stored in one address in the read-only memory 11. Then, in the next address, is stored the micro-command derive n-th numeric information from indicating register." Various microcommands, as shown in FIG. 3, are stored in the readonly memory 11 and used to carry out various operations step by step, automatically, unless there is no branch or jump command.

Next, referring to FIG. 4, the command and control portions are stored in one address in the read-only memory 11. For example, the micro-command 1001 stored in the control portion means transfer the content in the data portion into the register 12 When the address A is selected as shown in FIG. 4, the control signa hown in FIG. 5 is generated to open the AND gates 12, so that the digit information 1100 in the data portion is transferred to and stored in the register 12 The content in the register 12 is decoded by the anode driver 13A,; so that the anode in the l2-th digit is selected and energized. Instead of a diode matrix, the read-only memory 11 comprises core memories, or the like.

we claim:

1. A display control device for a numeric display unit comprising:

a shift register (15) having input and output terminals for storing a binary coded numeric information from the input terminals;

the numeric display unit (13) having a plurality of digit segments and a plurality of numeric segments in each of said digit segments for displaying the information stored in said shift register;

a digit segment drive circuit (l3A connected to said digit segments of said numeric display unit for selectively energizing said digit segments, said digit segment drive circuit including a first decoder for decoding a plurality of binary codes entered and for selecting one of said digit segments;

a numeric segment drive circuit (131( for selectively energizing said plurality of numeric segments associated with each of said digit segments, said numeric segment drive circuit including a second decoder for decoding a plurality of binary codes entered and for selecting some or all of said numeric segments;

a digit information buffer circuit (12,) having output terminals connected to the input terminals of said digit segment drive circuit;

a first group of AND gates (12,) having output terminals connected to the input terminals of said digit information buffer circuit and each having two input terminals;

a numeric information buffer circuit (14 having output tenninals connected to the input terminals of said numeric segment drive circuit;

a second group of AND gates (14 having output terminals connected to the input terminals of said numeric information buffer circuit and each having two input terminals;

an arithmetic unit (18) having output terminals for executing an arithmetic operation and for delivering the operational result to said shift register;

a readonly memory (11) composed of a semiconductor large scale integration circuit having at least a data portion including digit position information stored and a control portion including gate control signal stored therein;

means for controlling said first group of AND gates to deliver a digit position information signal to said digit information buffer circuit in response to an application of the digit position information from said data position of said read-only memory to one set of said input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of said input terminals thereof;

means for controlling said second group of AND gates to deliver a binary numeric information signal to said numeric information buffer circuit in response to an application of one digit numeric information from said shift register to one set of input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of input terminals thereof;

means for controlling said numeric display unit so that said plurality of digit segments are sequentially energized in accordance with the sequence of the digit information stored in said read-only memory and said numeric segments are selectively energized to display the numeric information stored in said shift register in accordance with the gate control signal included in said read-only memory, thereby to display plural digits of numerics on a time division basis.

2. A display control device as defined in claim 1, the

device further comprises:

a decimal point buffer circuit (16 for storing a decimal point position information to indicate a decimal point on said numeric display unit,

a third group of AND gates (16,) having output terminals connected to the input terminals of said decimal point buffer circuit and two sets of input terminals one set of which is connected to said shift register and the other set of input terminals is connected to said read-only memory to receive the gate control signal therefrom; and

a coincidence circuit (17) to which is applied the decimal point position information from said decimal point buffer circuit and the digit information from said digit information buffer circuit, thereby to display the decimal point on said numeric display unit on a time division basis.

3. A display control device as defined in claim 1, the

device further comprises:

a numeric information intermediate buffer circuit (14 connected between said numeric information buffer circuit (14 and the output terminals of said shift register;

a fourth group of AND gates (14 having output terminals connected to the input terminals of said numeric information intermediate buffer circuit and two sets of input terminals one set of which is applied with the numeric information from said shift register and the other set of input terminals is applied with the gate control signal from said readonly memory;

a first OR gate (2l) to which is applied the output from said numeric information intermediate buffer circuit (14 a second OR gate (19) to which is applied the output from said first OR gate (21);

a flip-flop (20) a set input of which is applied with the output of said second OR gate (19); and

a fifth group of AND gates (22) having one set of input terminals to which is applied a set output from said flip-flop and the other set of input terminals to which are applied outputs from said numeric segment drive circuit (13K thereby to generate at the output of said fifth group of AND gates a signal for suppressing an insignificant zero or zeros to be displaced in higher significant digit or digits thtn the significant digit.

4. A display control device as defined in claim 3, wherein said second OR gate (19) has a further input terminal to which is applied the output from said coincidence circuit (17) to set said flip-flop, thereby to display a zero in a digit associated with the decimal point. =1:

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,858,197 Dated December 31, 1974 Inventor) MITSUO SHIMIZU, ET AL.

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 2, line 19, "drawing" 'should read -drawings--;

Column 2, line 36, "from" should read -form-;

Column 2, line 61, "coindidence" should read coincidence;

Column 3, line 31, "energizes should read -energize--;

Column 3, line 47, "predetermained" should read predetermined-;

Column 3, line 64, "'coindidence" should read coincidence;

Column 3, line 65, "coindides" should read -coincides-;

Claim 1, Column 6, line 58, (12 should read (l2)-;

Claim 3, Column 8, line 41, "thtn" should read --than--.

Signed and sealed this 6th day of May 1975.

(SEAL) Attest:

C. MARSHALL DANN RUTH C. MASON Commissioner of Patents Attesting Officer and Trademarks FORM PO-IOSO (IO-69) USCOMM'DC 60376-P69 U. S. GOVERNMENT PRINTING OFFICE "I, 0-366-33, 

1. A display control device for a numeric display unit comprising: a shift register (15) having input and output terminals for storing a binary coded numeric information from the input terminals; the numeric display unit (13) having a plurality of digit segments and a plurality of numeric segments in each of said digit segments for displaying the information stored in said shift register; a digit segment drive circuit (13AD) connected to said digit segments of said numeric display unit for selectively energizing said digit segments, said digit segment drive circuit including a first decoder for decoding a plurality of binary codes entered and for selecting one of said digit segments; a numeric segment drive circuit (13KD) for selectively energizing said plurality of numeric segments associated with each of said digit segments, said numeric segment drive circuit including a second decoder for decoding a plurality of binary codes entered and for selecting some or all of said numeric segments; a digit information buffer circuit (121) having output terminals connected to the input terminals of said digit segment drive circuit; a first group of AND gates (121) having output terminals connected to the input terminals of said digit information buffer circuit and each having two input terminals; a numeric information buffer circuit (144) having output terminals connected to the input terminals of said numeric segment drive circuit; a second group of AND gates (143) having output terminals connected to the input terminals of said numeric information buffer circuit and each having two input terminals; an arithmetic unit (18) having output terminals for executing an arithmetic operation and for delivering the operational result to said shift register; a read-only memory (11) composed of a semi-conductor large scale integration circuit having at least a data portion including digit position information stored and a control portion including gate control signal stored therein; means for controlling said first group of AND gates to deliver a digit position information signal to said digit information buffer circuit in response to an application of the digit position information from said data position of said read-only memory to one set of said input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of said input terminals thereof; means for controlling said second group of AND gates to deliver a binary numeric information signal to said numeric information buffer circuit in response to an application of one digit numeric information from said shift register to one set of input terminals thereof as well as an application of the gate control signal from said control portion of said read-only memory to the other set of input terminals thereof; means for controlling said numeric display unit so that said plurality of digit segments are sequentially energized in accordance with the sequence of the digit information stored in said read-only memory and said numeric segments are selectively energized to display the numeric information stored in said shift register in accordance with the gate control signal included in said read-only memory, thereby to display plural digits of numerics on a time division basis.
 2. A display control device as defined in claim 1, the device further comprises: a decimal point buffer circuit (162) for storing a decimal point position information to indicate a decimal point on said numeric display unit, a third group of AND gates (161) having output terminals connected to the input terminals of said decimal point buffer circuit and two sets of input terminals one set of which is connected to said shift register and the other set of input terminals is connected to said read-only memory To receive the gate control signal therefrom; and a coincidence circuit (17) to which is applied the decimal point position information from said decimal point buffer circuit and the digit information from said digit information buffer circuit, thereby to display the decimal point on said numeric display unit on a time division basis.
 3. A display control device as defined in claim 1, the device further comprises: a numeric information intermediate buffer circuit (142) connected between said numeric information buffer circuit (144) and the output terminals of said shift register; a fourth group of AND gates (141) having output terminals connected to the input terminals of said numeric information intermediate buffer circuit and two sets of input terminals one set of which is applied with the numeric information from said shift register and the other set of input terminals is applied with the gate control signal from said read-only memory; a first OR gate (21) to which is applied the output from said numeric information intermediate buffer circuit (142); a second OR gate (19) to which is applied the output from said first OR gate (21); a flip-flop (20) a set input of which is applied with the output of said second OR gate (19); and a fifth group of AND gates (22) having one set of input terminals to which is applied a set output from said flip-flop and the other set of input terminals to which are applied outputs from said numeric segment drive circuit (13KD), thereby to generate at the output of said fifth group of AND gates a signal for suppressing an insignificant zero or zeros to be displaced in higher significant digit or digits thtn the significant digit.
 4. A display control device as defined in claim 3, wherein said second OR gate (19) has a further input terminal to which is applied the output from said coincidence circuit (17) to set said flip-flop, thereby to display a zero in a digit associated with the decimal point. 